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symmetric multiprocessor system : ウィキペディア英語版
symmetric multiprocessor system

A symmetric multiprocessor system (SMP) is a multiprocessor system with centralized shared memory called ''main memory'' (MM) operating under a ''single'' operating system with two or more homogeneous processors—i.e., it is ''not'' a heterogeneous computing system.
More precisely, an SMP is a tightly coupled multiprocessor system with a pool of homogeneous processors running independently, each processor executing different programs and working on different data, with the capability to share resources (memory, I/O device, interrupt system, etc.), and connected using a system bus or a crossbar.〔"An Introduction to the New IBM e-server pSeries High Performance Switch" - ''Glossary pg. 246'' - http://www.redbooks.ibm.com/redbooks/pdfs/sg246978.pdf〕〔Locking in OS Kernels for SMP Systems - http://irl.cs.ucla.edu/~yingdi/web/paperreading/smp_locking.pdf〕〔(【引用サイトリンク】title=Patent US6349369 - Protocol for transferring modified-unsolicited state during data intervention )
Each processor usually has an associated private high-speed memory known as cache memory (or cache) to speed-up the MM data access and to reduce the system bus traffic.
== Terminology ==
Sometimes the term "symmetric multiprocessor" is confused with the term symmetric multiprocessing.
While multiprocessing is a type of processing in which two or more processors work together to process more than one program simultaneously, the term "multiprocessor" refers to the hardware architecture that allows multiprocessing.
The term "multiprocessor" is the opposite of the term "uniprocessor".
The term "symmetric multiprocessor" is used in the majority of the technical papers.〔(【引用サイトリンク】title=Brevetto US8453122 - Symmetric multi-processor lock tracing )〕〔http://www8.cs.umu.se/kurser/5DV016/VT09/assignments/A2/mm.pdf〕〔 Intel MultiProcessor Specification - 2. System Overview - http://pdos.csail.mit.edu/6.828/2007/readings/ia32/MPspec.pdf〕〔(【引用サイトリンク】title=Patent US7103631 - Symmetric multi-processor system )〕〔http://www.uspto.gov/web/patents/patog/week06/OG/html/1387-1/US08370595-20130205.html〕〔http://www.uspto.gov/web/patents/patog/week49/OG/html/1385-1/US08327372-20121204.html〕

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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